Xiaokun Yang

Xiaokun Yang, Ph.D.

Assistant Professor of Computer Engineering,
College of Science and Engineering

Contact number: 281-283-3812
Email: yangxia@uhcl.edu
Office: Delta Annex 10

Biography

Dr. Xiaokun Yang received his Ph.D. from the Department of Electrical and Computer Engineering (ECE), Florida International University (FIU), USA in Spring 2016, his dual M.S. from the Department of ECE at FIU and the Department of Software Engineering at Beihang University, China in 2007. He is currently an Assistant Professor at the College of Science and Engineering, University of Houston, Clear Lake.

From 2007 to 2012, he has also worked as a Senior ASIC Design/Layout Engineer at Advanced Micro Devices (AMD), China Electronic Corporation (CEC), and PowerLayer MicroSystems (PLM). His chip tape-out experiences include AMD CPUs/APUs (Kabini, Kaveri, Bonaire, Kryptos, and Samara), 802.11 a/b/g/n MIMO mixed-signal SoCs (CEC TL3 and TL5), and PLM high-definition TV (HDTV) SoCs (PLM3K and PLM5K).

Dr. Xiaokun Yang received his Ph.D. from the Department of Electrical and Computer Engineering (ECE), Florida International University (FIU), USA in Spring 2016, his dual M.S. from the Department of ECE at FIU and the Department of Software Engineering at Beihang University, China in 2007. He is currently an Assistant Professor at the College of Science and Engineering, University of Houston, Clear Lake.

From 2007 to 2012, he has also worked as a Senior ASIC Design/Layout Engineer at Advanced Micro Devices (AMD), China Electronic Corporation (CEC), and PowerLayer MicroSystems (PLM). His chip tape-out experiences include AMD CPUs/APUs (Kabini, Kaveri, Bonaire, Kryptos, and Samara), 802.11 a/b/g/n MIMO mixed-signal SoCs (CEC TL3 and TL5), and PLM high-definition TV (HDTV) SoCs (PLM3K and PLM5K).


Publications

  1. X. Yang and J. Andrian, "An Advanced Bus Architecture for AES-Encrypted High-Performance Embedded Systems," US Patent, US20170302438A1, Oct. 19, 2017.
  2. X. Yang, W. Wen, and M. Fan, "Improving AES Core Performance via An Advanced IBUS Protocol," ACM Journal on Emerging Technologies in Computing (JETC - IF: 0.803), Vol. 14, No. 1, PP. 61-63 , Jan. 2018. doi>10.1145/3110713
  3. X. Yang and W. Wen, "Design of A Pre-Scheduled Data Bus (DBUS) for Advanced Encryption Standard (AES) Encrypted System-on-Chips (SoCs)," The 22nd Asia and South Pacific Design Automation Conference, (ASP-DAC 2017 - Regular Paper, Acceptance Rate:111/358=31%), PP. 506-511, Jan.  2017. doi>10.1109/ASPDAC.2017.7858373
  4. X. Yang, N. Wu, and J. Andrian, "Comparative Power Analysis of An Adaptive Bus Encoding Method on The MBUS Structure," Journal of VLSI Design, Vol. 2017, Article ID 4914301, PP. 1-7, May 2017. doi>https://doi.org/10.1155/2017/4914301
  5.  X. Yang and X. He, "Establishing a BLE Mesh Network using Fabricated CSRmesh Devices," The 2nd ACM/IEEE Symposium on Edge Computing (SEC 2017), Article No. 34, Oct. 2017. doi>10.1145/3132211.3132460
  6. X. Yang and N. Wu, "Design of A Bio-Feedback Digital System (BFS) Using 33-Step Training Table for Cardio Equipment," The 8th Intl. Conference on Applied Human Factors and Ergonomics (AHFE 2017), Vol. 603, PP. 53-64, June 2017. doi>10.1007/978-3-319-60822-8_5
  7. X. Yang, Y. Zhang, W. Wen, and M. Fan, "A Case Study of Self-Organization Algorithms for High-Efficiency System-on-Chips Integration," IEEE Intl. Conf. on Autonomic Computing (ICAC 2017) – Workshop on Feedback Computing, Accepted, In Press, July, 2017.
  8. M. Fan, Q. Han, and X. Yang, "Energy Minimization for On-Line Real-Time Scheduling with Reliability Awareness," Elsevier Journal of Systems and Software. (JSS IF: 1.424), Vol. 127, PP. 168-176, May 2017.
  9.  X. Yang, L. Wu, Y. Zhang, etc., "Exploiting Energy-Quality (E-Q) Tradeoffs: A Case Study of An Approximate FPGA Design," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS - IF: 2.542), Under Review, 2018.
  10. X. Yang, L. Wu, H. He, etc., "Towards High-Throughput and Low-Cost SoC Integration: A Case Study of Scalable Wrapper Designs on FPGAs," IET Computers & Digital Techniques (CDT - IF: 0.589), Under Review, 2018.


Courses (Current Academic Year)

 Graduate course

  • CENG 5534 Advanced Digital System Design

Undergraduate course

  • CENG 4345 Digital System Design
  • CENG 3316 Electronics
  • CENG 3116 Electronics Lab


Research Projects

  • Approximate Design on Fog/Edge System
  • Energy-Quality (E-Q) Tradeoff on ASIC/FPGA Design
  • Low-Cost and Low-Energy SoC Architecture on IoT
  • Integrated Circuit Design and Verification Methodology


Awards and Accomplishments

  • PI: Cisco Research & Open Innovation, Pending, 2017-2018
  • PI: Faculty Research and Support Funds (FRSF), 2017-2018
  • PI: Faculty Development Funds: ICAC2017, ASAP2017, SEC2017
  • NSF Travel Grant, IEEE Intl. Conf. on Autonomic Computing (ICAC), 2017
  • NSF Travel Grant, ACM/IEEE Symposium on Edge Computing (SEC 2017), 2017
  • Section Chairs: ICCAS2018, IEEE Innovation and Automation Conference, etc.
  • TPC member: MicDAT2018; Nanoarch2017; WCSE2018; etc.
  • Journal Reviewer: TVLSI; TII; IET CDT; Integration, the VLSI; etc.